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18-bit 250/670 ksps pulsar ? bipolar programmable inputs adc preliminary technical data AD7631/ad7634 rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features multiple pins/software programmable input ranges: 10v, 5v, 10v, 5v i cmos? process technology pins or serial spi input ranges/mode selection throughput: 670ksps (ad7634) 250ksps (AD7631) inl: 1.75 lsb (7 ppm of full scale) dnl: +2/-1 lsb 18-bit resolution with no missing codes dynamic range: 102.5 db typical snr: 101 db typical thd: -122 db typical 5v internal reference: typical drift 7ppm/c; temp output no pipeline delay (sar architecture) parallel (18, 16- or 8-bit bus) and serial 5 v/3.3 v interface spi?-/qspi?-/microwire?-/dsp-compatible power dissipation: 190 mw @ 670ksps 75 mw @ 250ksps pb-free 48-lead lqfp and lfcsp (7x7mm) packages pin compatible with other pulsar adcs applications process control high speed data acquisition digital signal processing spectrum analysis instrumentation communications general description the AD7631/ad7634 is an18-bit, charge redistribution successive approximation register (sar) architecture analog-to- digital converter (adc) with programmable input ranges and mode selection via a dedicated write only serial interface (or by hardware pin-strapping). the device is fabricated on adis patented i cmos high voltage process. the device contains a high speed 18-bit sampling adc, an internal conversion clock, an internal reference (and buffer), and both serial and parallel system interface ports. power consumption is automatically scaled with throughput (ad7634 in impulse mode), making it ideal for battery-powered applications. it is available in pb-free, 48-lead packages with operation specified from ?40c to +85c. functional block diagram -001 18 control logic and calibration circuitry clock AD7631/ ad7634 dgnd dvdd avdd agnd ref refgnd in+ in- pd reset cnvst pdbuf refbufin pdref ref temp d[17:0] busy rd cs d0/ob/2c ognd ovdd ref amp serial data port parallel interface switched cap dac vcc vee warp impulse serial programmable port sppdata sppclk sppen hw/sw mode0 mode1 figure 1. table 1. pulsar? selection type/ksps 100 to 250 500 to 570 650 to 1000 >1000 pseudo differential ad7651 , ad7660 ad7661 ad7650 ad7652 ad7664 ad7666 ad7653 ad7667 true bipolar ad7610 , ad7663 ad7665 ad7612 , ad7671 true differential ad7675 ad7676 ad7677 ad7621 ad7622 ad7623 18-bit multichannel/ AD7631 ad7678 ad7679 ad7634 ad7674 ad7641 ad7643 simultaneous ad7654 ad7655 product highlights 1. programmable input range and mode selection. dedicated write only serial port used for selecting input range and mode select (mode select ad7634 only). 2. fast throughput the ad7634 is 670ksps and the AD7631 is 250ksps. 3. superior linearity. no missing 18-bit code. +/- 1.75 lsb typical inl 4. internal reference. 5 v internal reference with a typical drift of 7 ppm/c and on-chip temp sensor. 5. serial or parallel interface. versatile parallel (18, 16- or 8-bit bus) or 2-wire serial interface arrangement compatible with 3.3 v, or 5 v logic.
AD7631/ad7634 preliminary technical data rev. prc | page 2 of 14 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 6 absolute maximum ratings ............................................................8 esd caution ...................................................................................8 pin configuration and function descriptions ..............................9 ter mi nolo g y .................................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history
preliminary technical data AD7631/ad7634 rev. prc | page 3 of 14 specifications avdd = dvdd = 5 v; ovdd = 2.7 v to 5.5 v; vcc = 15v; vee = -15v; v ref = 5 v; all specifications t min to t max , unless otherwise noted. table 2. parameter conditions min typ max unit resolution 18 bits analog input t 1 differential voltage range 0 to 5v v in+ - v in? -v ref v ref 0 to 10v v in+ - v in? -2v ref 2v ref 5v v in+ - v in? -2v ref 2v ref 10v v in+ - v in? -4v ref 4v ref operating input voltage range 0 to 5v (v in+, v in? ) to agnd -0.1v v ref + 0.1v 0 to 10v (v in+, v in? ) to agnd -0.1v 2v ref + 0.1v 5v (v in+, v in? ) to agnd -v ref C 0.1v v ref + 0.1v 10v (v in+, v in? ) to agnd -2v ref C 0.1v 2v ref + 0.1v common mode voltage range 0 to 5v v in+ , v in? v ref /2 C 0.1v v ref /2 v ref /2 + 0.1v 0 to 10v v in+ , v in? v ref C 0.2v v ref v ref + 0.2v bipolar ranges v in+ , v in? C0.1v 0 0.1v analog input cmrr f in = 100 khz tbd db input current @ 670 ksps throughput tbd a input current @ 250 ksps throughput tbd a input impedance throughput speed complete cycle ad7634 in warp mode 1.49 s throughput rate ad7634 in warp mode 1 670 ksps time between conversions ad7634 in warp mode 1 ms complete cycle ad7634 in normal mode 1.75 s throughput rate ad7634 in normal mode 0 570 ksps complete cycle ad7634 in impulse 2.22 s throughput rate ad7634 in impulse mode 0 450 ksps complete cycle AD7631 4 s throughput rate AD7631 0 250 ksps dc accuracy integral linearity error 2 v ref = 5v, pdref = pdbuf = high 1.75 lsb 3 no missing codes 18 bits differential linearity error ?1 +2 lsb transition noise 0.75 lsb bipolar offset error 10 lsb bipolar offset error temperature drift tbd ppm/c bipolar full-scale error 60 lsb bipolar full-scale error temperature drift tbd ppm/c power supply sensitivity avdd = 5 v 5% tbd lsb
AD7631/ad7634 preliminary technical data rev. prc | page 4 of 14 parameter conditions min typ max unit ac accuracy dynamic range v in = 5v, f in = 2 khz, -60db 102.5 db 4 signal-to-noise v in = 5v, f in = 2 khz 101 db spurious-free dynamic range v in = 5v, f in = 2 khz 122 db total harmonic distortion v in = 5v, f in = 2 khz -106 db signal-to-(noise + distortion) v in = 5v, f in = 2 khz 100 db C3 db input bandwidth 12 mhz sampling dynamics aperture delay 1 ns aperture jitter 5 ps rms transient response full-scale step 115 ns internal reference pdref = pdbuf = low output voltage ref @ 25c 4.985 5.000 5.015 v temperature drift C40c to +85c 7 ppm/c line regulation avdd = 5 v 5% 15 ppm/v turn-on settling time c ref = 10 f 5 ms r eference buffer pdref = high refbufin input voltage range 2.5 v external reference pdref = pdbuf = high voltage range ref 5 avdd+0.1 v current drain ad7634 @ 670 ksps throughput tbd a current drain AD7631 @ 250 ksps throughput tbd a temperature pin voltage output temp @ 25c tbd mv temperature sensitivity 1 mv/c output resistance 4 k digital inputs logic levels v il C0.3 +0.6 v v ih 2.1 ovdd+0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format 5 pipeline delay 6 v ol i sink = 500 a 0.4 v v oh i source = ?500 a ovdd ? 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v vcc 15 v vee -15 v
preliminary technical data AD7631/ad7634 rev. prc | page 5 of 14 parameter conditions min typ max unit operating current 7 pdref = pdbuf = low avdd 8 AD7631 @ 250ksps throughput 8.5 ma ad7634 @ 670ksps throughput 21 ma dvdd AD7631 @ 250ksps throughput 3.5 ma ad7634 @ 670ksps throughput 7 ma ovdd AD7631 @ 250ksps throughput 0.1 ma ad7634 @ 670ksps throughput 0.2 ma vcc AD7631 @ 250ksps throughput 1 ma vee AD7631 @ 250ksps throughput 0.6 ma vcc ad7634 @ 670ksps throughput 2.8 ma vee ad7634 @ 670ksps throughput 2 ma power dissipation with internal reference 7 AD7631 @ 250ksps throughput 75 mw with internal reference 7 ad7634 @ 670ksps throughput 190 without internal reference AD7631 @ 250ksps throughput 62 mw without internal reference 7 ad7634 @ 670ksps throughput 160 mw in power-down mode 9 pd = high 2 w temperature range 10 specified performance t min to t max ?40 +85 c 1 the inputs are differential anti-phase. refer to the error! reference source not found. section. 2 linearity is tested using endnotes, not best fit. 3 lsb means least significant bit. with the 0 to 5v input range, 1 lsb 38.15v. 4 all specifications in db are referred to a full-scale input fsr. tested with an input signal at 0.5 db below full-scale, unles s otherwise specified. 5 parallel or serial 18-bit. 6 conversion results are available imme diately after completed conversion. 7 tested in parallel reading mode. 8 with internal reference, pdref and pdbuf are low; without internal re ference, pdref and pdbuf are high. 9 with all digital inputs forced to ovdd. 10 consult sales for extended temperature range.
AD7631/ad7634 preliminary technical data rev. prc | page 6 of 14 timing specifications avdd = dvdd = 5 v; ovdd = 2.7 v to 5.5 v; vcc = 15v; vee = -15v; v ref = 5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit conversion and reset convert pulse width t 1 10 ns time between conversions (warp mode/normal mode 1 ) t 2 ns AD7631 4 s ad7634 (warp mode/normal mode/impulse mode) 2 1.49/1.75/2.22 s cnvst low to busy high delay t 3 35 ns busy high all modes (except master serial read after convert) t 4 AD7631 tbd s ad7634 (warp mode/normal mode/impulse mode) tbd s aperture delay t 5 2 ns end of conversion to busy low delay t 6 10 ns conversion time t 7 AD7631 tbd s ad7634 (warp mode/normal mode/impulse mode) tbd s acquisition time t 8 AD7631 250 ns ad7634 (warp mode/normal mode/impulse mode) 250 ns reset pulse width t 9 10 ns parallel interface modes cnvst low to data valid delay t 10 AD7631 1.5 s ad7634 (warp mode/normal mode/impulse mode) 1/1.25/1.5 s data valid to busy low delay t 11 12 ns bus access request to data valid t 12 45 ns bus relinquish time t 13 5 15 ns master serial interface modes 3 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 AD7631 525 ns ad7634 (warp mode/normal mode/impulse mode) 25/275/525 ns sync asserted to sclk first edge delay t 18 3 ns internal sclk period 4 t 19 25 40 ns internal sclk high 4 t 20 12 ns internal sclk low 4 t 21 7 ns sdout valid setup time 4 t 22 4 ns sdout valid hold time 4 t 23 2 ns sclk last edge to sync delay 4 t 24 3 ns cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns
preliminary technical data AD7631/ad7634 rev. prc | page 7 of 14 parameter symbol min typ max unit busy high in master serial read after convert 4 t 28 see table 4 cnvst low to sync asserted delay (all modes) t 29 ns AD7631 tbd ns ad7634 (warp mode/normal mode/impulse mode) tbd ns sync deasserted to busy low delay t 30 25 ns slave serial interface modes external sclk setup time t 31 5 ns external sclk active edge to sdout delay t 32 1 8 ns sdin setup time t 33 5 ns sdin hold time t 34 5 ns external sclk period t 35 12.5 ns external sclk high t 36 5 ns external sclk low t 37 5 ns 1 in warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 in warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 3 in serial interface modes, the sync, sclk, an d sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 4 in serial master read during convert mode. see error! reference source not found. for serial master read after conv ert mode timing specifications. table 4. serial clock timings in master read after convert mode divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 18 3 17 17 17 ns internal sclk period minimum t 19 25 60 120 240 ns internal sclk period maximum t 19 40 80 160 320 ns internal sclk high minimum t 20 12 22 50 100 ns internal sclk low minimum t 21 7 21 49 99 ns sdout valid setup time minimum t 22 4 18 18 18 ns sdout valid hold time minimum t 23 2 4 30 89 ns sclk last edge to sync delay minimum t 24 3 60 140 300 ns busy high width maximum (warp mode) t 28 1.75 2.5 4 7 s busy high width maximum (normal mode) t 28 2 2.75 4.25 7.25 s busy high width maximum (impulse mode) t 28 2.25 3 4.5 7.5 s
AD7631/ad7634 preliminary technical data rev. prc | page 8 of 14 absolute maximum ratings table 5. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog inputs/outputs in+, in?, ref, refbufin, temp, ingnd, refgnd to agnd avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd ?0.3 v to +2.7 v ovdd ?0.3 v to +3.8 v avdd to dvdd 2.8 v avdd, dvdd to ovdd ?3.8 v to +2.8 v digital inputs ?0.3 v to +5.5 v pdref, pdbuf 20 ma internal power dissipation 700 mw 1 internal power dissipation 2.5 w 2 junction temperature 125c storage temperature range C65c to +125c 1. specification is for the device in free air: 48-lead lqfp; ja = 91c/w, jc = 30c/w. 2. specification is for the device in free air: 48-lead lfcsp; ja = 26c/w. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 04761-002 note in serial interface modes, the sync, sclk, and sdout timing are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. 500 ai ol 500 ai oh 1.4v to output pin c l 50pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay 04761-003 figure 3. voltage reference levels for timing figure 2. load circuit for digital interface timing, sdout, sync, and sclk outputs, c = 10 pf l
preliminary technical data AD7631/ad7634 rev. prc | page 9 of 14 pin configuration and function descriptions 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) bipolar cnvst pd reset cs rd ten agnd avdd mode0 mode1 d0/ob/2c nc = no connect d1/a0 d3 d4divsclk[0] busy d17/sppen d16/sppclk d15/sppdata AD7631/ad7634 d5/divsclk[1] d14/hw/sw d6/ext/int d7/invsync d8/invsclk d9/rdc/sdin ognd ovdd dvdd dgnd d10/sdout d11/sclk d12/sync d13/rderror pdbuf pdref refbufin temp avdd in+ agnd vee vcc in? refgnd ref impulse warp -004 d2/a1 figure 4. pin configuration table 6. pin function descriptions pin no. description mnemonic type 1 1, 42 agnd p analog power ground pin. 2, 44 avdd p input analog power pins. nominally 5 v. 3, 4 mode[0:1] di data output interface mode selection. interface mode# mode1 mode0 description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 serial interface 5 d0/ob/ 2c di/o when mode[1:0] = 0 (18-bit interface mode), this pi n is bit 0 of the parallel port data output bus and the data coding is straight binary. in all other modes, this pin allows the choice of straight binary/twos complement. when ob/ 2c is high, the digital output is straight binary; when low, the msb is inverted resulting in a twos complement output from its internal shift register. 6 warp di ad7634: conversion mode selection. when warp = high and impulse = low, this selects warp mode. in this mode, the maximum throughput is achievable , and a minimum conversion rate must be applied to guarantee full specified accuracy. when warp = low and impulse = low, this selects normal mode where full accuracy is maintained independent of the minimum conversion rate. AD7631: connect to dgnd. 7 impulse di ad7634: conversion mode selection. when impulse = high and warp = low, this input selects impulse mode, a reduced power mode. in this mode, the power dissipation is approximately scaled proportional to the sampling rate. AD7631: connect to dgnd. 8 d1/a0 di/o when mode[1:0] = 0, this pin is bit 1 of the paralle l port data output bus. in all other modes, this input pin controls the form in which data is output as shown in table 7 . 9 d2/a1 di/ o when mode[1:0] = 0, this pin is bit 2 of the parallel port data output bus. when mode[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in table 7 . 10 d3 d0 when mode[1:0] = 0, 1, or 2, this output is used as bit 3 of the parallel port data output bus. this pin is always an output, re gardless of the interface mode.
AD7631/ad7634 preliminary technical data rev. prc | page 10 of 14 pin no. mnemonic type 1 description 11, 12 d[4:5] di/o when mode[1:0] = 0, 1, or 2, these pi ns are bit 4 and bit 5 of the parallel port data output bus. or divsclk[0:1] when mode[1:0] = 3 (serial mode), serial clock divi sion selection. when using serial master read after convert mode (ext/ int = low, rdc/sdin = low), these inputs can be used to slow down the internally generated serial clock that clocks the da ta output. in other serial modes, these pins are high impedance outputs. 13 d6 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 6 of the para llel port data output bus. or ext/ int when mode[1:0] = 3 (serial mode), serial clock source select. this input is used to select the internally generated (master) or external (slave) serial data clock. when ext/ int = low, master mode. the internal serial clock is selected on sclk output. when ext/ int = high, slave mode. the output data is sync hronized to an external clock signal, gated by cs , connected to the sclk input. 14 d7 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 7 of the para llel port data output bus. or invsync when mode[1:0] = 3 (serial mode), invert sy nc select. in serial master mode (ext/ int = low), this input is used to select the active state of the sync signal. when invsync = low, sync is active high. when invsync = high, sync is active low. 15 d8 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 8 of the para llel port data output bus. or invsclk when mode[1:0] = 3, invert sclk select. in all serial modes, this input is used to invert the sclk signal. 16 d9 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 9 of the parall el port data output bus. or rdc when mode[1:0] = 3 (serial mode), read during convert. when using serial master mode (ext/ int = low), rdc is used to select the read mode. when rdc = high, the previous conversion result is output on sdout during conversion and the period of sclk changes. when rdc = low (read after convert), the current result can be output on sdout only when the conversion is complete. or sdin when mode[1:0] = 3 (serial mode), serial da ta in. when using serial slave mode, (ext/ int = high), sdin could be used as a data input to daisy-chai n the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 18 sclk periods after the initiation of the read sequence. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (2.7 v to 5v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground. 21 d10 do when mode[1:0] = 0, 1, or 2, this output is used as bit 10 of the parallel port data output bus. or sdout when mode[1:0] = 3 (serial mode), se rial data output. in se rial mode, this pin is used as the serial data output synchronized to sclk. conversion results are stored in an on-chip register. the adc provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in master mode, ext/ int = low. sdout is valid on both edges of sclk. in slave mode, ext/ int = high: when invsclk = low, sdout is updated on sclk ri sing edge and valid on the next falling edge. when invsclk = high, sdout is updated on sclk fa lling edge and valid on the next rising edge. 22 d11 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 11 of the parallel port data output bus. or sclk when mode[1:0] = 3 (serial mode), serial clock. in all serial modes, this pin is used as the serial data clock input or output, dependin g upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends on the logic state of the invsclk pin. 23 d12 do when mode[1:0] = 0, 1, or 2, this output is used as bit 12 of the parallel port data output bus. or sync when mode[1:0] = 3 (serial mode), frame sync hronization. in serial master mode (ext/ int = low), this output is used as a digital output frame synchronization for use with the internal data clock.
preliminary technical data AD7631/ad7634 rev. prc | page 11 of 14 pin no. mnemonic type 1 description when a read sequence is initiated and invsync = low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync = high, sync is driven low and remains low while sdout output is valid. 24 d13 do when mode[1:0] = 0, 1, or 2, this output is used as bit 13 of the parallel port data output bus. or rderror when mode[1:0] = 3 (serial mode), read error. in serial slave mode (ext/ int = high), this output is used as an incomplete read error flag. if a data read is started and not completed when the current conversion is complete, the current data is lost and rderror is pulsed high. 25 d14 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 14 of the parallel port data output bus. or hw/ sw when mode[1:0] = 3 (serial mode) hardware/softw are select. this input, part of the serial programmable port, is used to select hardware or software input ranges and mode selection. 26 d15 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 15 of the parallel port data output bus. or sppdata when mode[1:0] = 3 (serial mode), serial programmabl e port data. this input is used to write in the serial programmable port data when hw/ sw = low. 27 d16 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 16 of the parallel port data output bus. or sppclk when mode[1:0] = 3 (serial mode), serial programmabl e port clock. this input is used to clock in the data on sppdata. the active edge where the data sppdata is updated depends on the logic state of the invsclk pin. 28 d17 di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 17 of the parallel port data output bus. or sppen when mode[1:0] = 3 (serial mode), serial programma ble port enable. asserting this input enables the serial programmable port. 29 busy do busy output. transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chi p shift register. the falling edge of busy can be used as a data-ready clock signal. 30 ten di 10 volt input range. refer to table 8 . when mode[1:0] = 0, 1, or 2, this input is used to select the 10v input range. when mode[1:0] = 3 (serial mode), and hw/ sw = high, driving ten high selects the 10 volt input range. hw/ sw = low, the input range is programmed with th e serial programmable port and this pin is a dont care. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the exte rnal clock in slave serial mode. 33 reset di reset input. when high, resets the adc. current co nversion, if any, is aborted. falling edge of reset enables the calibration mode indicated by pulsing busy high. if not used, this pin can be tied to dgnd. 34 pd di power-down input. when high, power downs the adc. power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di conversion start. a falling edge on cnvst puts the internal sample-and-hold into the hold state and initiates a conversion. 36 bip di bipolar input range. refer to table 8 . when mode[1:0] = 0, 1, or 2, this input is used to select the bipolar input range. when mode[1:0] = 3 (serial mode), and hw/ sw = high, driving bip high selects the bipolar input range. hw/ sw = low, the input range is programmed with th e serial programmable port and this pin is a dont care. 37 ref ai/o reference output/input. when pdref/pdbuf = low, the internal reference an d buffer are enabled producing 5 v on this pin. when pdref/pdbuf = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to avdd volts. decoupling is required with or without the internal reference and buffer.
AD7631/ad7634 preliminary technical data rev. prc | page 12 of 14 pin no. mnemonic type 1 description 38 refgnd ai reference input analog ground. 39 in? ai differential negative analog input; referenced to in+. 40 v cc p high voltage positive supply. 41 v ee p high voltage negative supply. 43 in+ ai differential positive analog input; referenced to in-. 45 temp ao temperature sensor analog output. 46 refbufin ai/o reference buffer input. when using an external reference with the internal buffer (pdbuf = low, pdref = high), applying 2.5v on this pin produces 5v on the ref pin. when using the internal reference (pdbuf = pdref = low), this pin should not be connected. 47 pdref di internal reference power-down input. when low, the internal reference is enabled (pdbuf also needs to be low). when high, the internal reference is powered down and an external reference must been used. 48 pdbuf di internal reference buffer power-down input. when low, the buffer is enabled (pdref also needs to be low). when high, the buffer is powered-down and an external reference must be used. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = dig ital output; p = power. table 7. data bus interface definition mode mode1 mode0 d0/ob/ 2c d1/a0 d2/a1 d[3] d[4:9] d[10:11] d[12:15] d[16:17] description 0 0 0 r[0] r[1] r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 18-bit parallel 1 0 1 ob/ 2c a0 = 0 r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 16-bit high word 1 0 1 ob/ 2c a0 = 1 r[0] r[1] all zeros 16-bit low word 2 1 0 ob/ 2c a0 = 0 a1 = 0 all hi-z r[10:11] r[12:15] r[16:17] 8-bit high byte 2 1 0 ob/ 2c a0 = 0 a1 = 1 all hi-z r[2:3] r[4:7] r[8:9] 8-bit mid byte 2 1 0 ob/ 2c a0 = 1 a1 = 0 all hi-z r[0:1] all zeros 8-bit low byte 2 1 0 ob/ 2c a0 = 1 a1 = 1 all hi-z all zeros r[0:1] 8-bit low byte 3 1 1 ob/ 2c all hi-z serial interface serial interface table 8. input range selection. parallel mode and serial hardware mode range bip ten hw/ sw (serial mode) 0 - 5v low low high 0 - 10v low high high 5v high low high 10v high high high all ranges 1 x x low 1 in serial mode (mode[1:0] = 3) when hw/ sw = low, the input ranges are defined by registers.
preliminary technical data AD7631/ad7634 rev. prc | page 13 of 14 terminology integral nonlinearity error (inl) total harmonic distortion (thd) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal to (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. gain error effective number of bits (enob) the first transition (from 00000 to 00001) should occur for an analog voltage ? lsb above the nominal negative full scale (19.073486 v for the 0 to 5v range). the last transition (from 11110 to 11111) should occur for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 0 to 5v v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. enob is a measurement of the resolution with a sine wave input. it is related to sinad and is expressed in bits by enob = [( sinad db ? 1.76)/6.02] aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. zero error transient resp onse the zero error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. the time required for the ad7641 to achieve its rated accuracy after a full-scale step function is applied to its input. reference voltage temperature coefficient dynamic range it is derived from the typical shift of output voltage at 25c on a sample of parts maximum and minimum reference output voltage (v ) measured at t , t(25c), and t . it is expressed in ppm/c using it is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. ref min max () () ( ) () () 6 10 c25 cppm/ ? ? = m in m a x ref ref ref ref tt v minvmaxv tcv signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. where: v ref ( max ) = maximum v at t ref min , t(25c), or t max v ref ( min ) = minimum v at t ref min , t(25c), or t max v ref (25 c ) = v ref at 25c t max = +85c t min = C40c
AD7631/ad7634 preliminary technical data rev. prc | page 14 of 14 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 5. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters compliant to jedec standards mo-220-vkkd-2 pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed p a d (bottom view) paddle connected to agnd. this connection is not required to meet the electrical performances. figure 6. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad7641bcpz ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 1 ad7641bcpzrl 1 ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 ad7641bstz 1 ?40c to +85c 48-lead low profile quad flat package (lqfp) st-48 ad7641bstzrl 1 ?40c to +85c 48-lead low profile quad flat package (lqfp) st-48 eval-ad7641cb evaluation board 2 eval-controlbrd3 controller board 3 t 1 z = pb-free part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd3 for evaluation/demonstrat ion purposes. 3 this board allows a pc to control and communicate with all analog devices, inc. evaluation boards ending in the cb designators . ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. ttt

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